integrated device technology, inc. description: the fct16374t/at/ct/et and fct162374t/at/ct/et 16-bit edge-triggered d-type registers are built using ad- vanced dual metal cmos technology. these high-speed, low-power registers are ideal for use as buffer registers for data synchronization and storage. the output enable (x oe ) and clock (xclk) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. flow-through organization of signal pins sim- plifies layout. all inputs are designed with hysteresis for improved noise margin. the fct16374t/at/ct/et are ideally suited for driving high-capacitance loads and low-impedance backplanes. the output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. the fct162374t/at/ct/et have balanced output drive with current limiting resistors. this offers low ground bounce, minimal undershoot, and controlled output fall timesC reduc- ing the need for external series terminating resistors. the fct162374t/at/ct/et are plug-in replacements for the fct16374t/at/ct/et and abt16374 for on-board bus inter- face applications. idt54/74fct16374t/at/ct/et idt54/74fct162374t/at/ct/et fast cmos 16-bit register (3-state) functional block diagram 1 o 1 1 oe 1 clk 1 d 1 2542 drw 01 to 7 other channels c d 2 o 1 2 oe 2 clk 2 d 1 to 7 other channels c d 2542 drw 01 the idt logo is a registered trademark of integrated device technology, inc. military and industrial temperature ranges february 1997 1997 integrated device technology, inc. 5.8 dsc-2542/9 1 features: common features: 0.5 micron cmos technology high-speed, low-power cmos replacement for abt functions typical t sk (o) (output skew) < 250ps low input and output leakage 1 m a (max.) esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) packages include 25 mil pitch ssop, 19.6 mil pitch tssop, 15.7 mil pitch tvsop and 25 mil pitch cerpack extended commercial range of -40 c to +85 c ? cc = 5v 10% features for fct16374t/at/ct/et: high drive outputs (-32ma i oh , 64ma i ol ) power off disable outputs permit ?ive insertion typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25 c features for fct162374t/at/ct/et: balanced output drivers: 24ma (commercial), 16ma (military) reduced system switching noise typical v olp (output ground bounce) < 0.6v at v cc = 5v,t a = 25 c for the latest information regarding this part, please contact idt's web site at http://www.idt.com or fax-on-demand service at (us)1-800-9-idt-fax / (international) 408-492-8391.
5.8 2 idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges pin configurations 1 o 1 gnd 1 o 3 v cc 1 oe gnd 2 o 2 gnd v cc gnd 1 o 2 1 o 4 1 o 5 1 o 6 1 o 7 1 o 8 2 o 1 2 o 3 2 o 4 2 o 5 2 o 7 2 o 8 2 o 6 2 oe 1 clk 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 1 d 7 1 d 8 2 d 1 2 d 2 2 d 3 2 d 4 v cc 2 d 5 2 d 7 2 d 8 2 d 6 2 clk gnd gnd gnd 39 29 30 31 32 33 34 35 36 37 38 25 26 27 28 48 47 41 42 43 44 45 46 40 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 2542 drw 04 cerpack top view e48-1 1 o 1 gnd 1 o 3 v cc 1 oe gnd 2 o 2 gnd v cc gnd 1 o 2 1 o 4 1 o 5 1 o 6 1 o 7 1 o 8 2 o 1 2 o 3 2 o 4 2 o 5 2 o 7 2 o 8 2 o 6 2 oe 1 clk 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 1 d 7 1 d 8 2 d 1 2 d 2 2 d 3 2 d 4 v cc 2 d 5 2 d 7 2 d 8 2 d 6 2 clk gnd gnd gnd 2542 drw 03 39 29 30 31 32 33 34 35 36 37 38 25 26 27 28 48 47 41 42 43 44 45 46 40 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 ssop/ tssop/tvsop top view so48-1 so48-2 so48-3
idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges 5.8 3 pin description function table (1) absolute maximum ratings (1) capacitance (t a = +25 c, f = 1.0mhz) 2542 tbl 01 2542 tbl 02 note: 1. this parameter is measured at characterization but not tested. 2542 lnk 04 symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6.0 pf c i/o i/o capacitance v out = 0v 3.5 8.0 pf pin names description xdx data inputs xclk clock inputs xox 3-state outputs. x oe 3-state output enable input (active low) inputs outputs function xdx xclk x oe oe xox hi-z x l h z xhhz load l - ll register h - lh l - hz h - hz note: 1. h = high voltage level l = low voltage level x = dont care z = high impedance - = low-to-high transition symbol description max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C60 to +120 ma notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxxt output and i/o terminals. 3. output and i/o terminals for fct162xxxt. 2542 lnk 03
5.8 4 idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40 c to +85 c, v cc = 5.0v 10%; military: t a = C55 c to +125 c, v cc = 5.0v 10% 2542 lnk 07 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25 c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. the test limit for this parameter is 5 m a at t a = C55 c. symbol parameter test conditions (1) min. typ. (2) max. unit i odl output low current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) 60 115 200 ma i odh output high current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) C60 C115 C200 ma v oh output high voltage v cc = min. v in = v ih or v il i oh = C16ma mil. i oh = C24ma com'l. 2.4 3.3 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 16ma mil. i ol = 24ma com'l. 0.3 0.55 v symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i i h input high current (input pins) (5) v cc = max. v i = v cc 1 m a input high current (i/o pins) (5) 1 i i l input low current (input pins) (5) v i = gnd 1 input low current (i/o pins) (5) 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 m a i ozl (3-state output pins) (5) v o = 0.5v 1 v ik clamp diode voltage v cc = min., i in = C18ma C 0.7 C 1.2 v i os short circuit current v cc = max., v o = gnd (3) C80 C 140 C 250 ma v h input hysteresis 100 mv i ccl i cch i ccz quiescent power supply current v cc = max., v in = gnd or v cc 5 500 m a 2542 lnk 05 symbol parameter test conditions (1) min. typ. (2) max. unit i o output drive current v cc = max., v o = 2.5v (3) C50 C 180 ma v oh output high voltage v cc = min. i oh = C3ma 2.5 3.5 v v in = v ih or v il i oh = C12ma mil. i oh = C15ma com'l. 2.4 3.5 v i oh = C24ma mil. i oh = C32ma com'l. (4) 2.0 3.0 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 48ma mil. i ol = 64ma com'l. 0.2 0.55 v i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v 1 m a output drive characteristics for fct16374t output drive characteristics for fct162374t 2542 lnk 06
idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges 5.8 5 power supply characteristics 2542 tbl 08 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp n cp /2 + f i n i ) i cc = quiescent current (i ccl , i cch and i ccz ) d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 1.5 ma i ccd dynamic power supply current (4) v cc = max. outputs open x oe = gnd one input toggling 50% duty cycle v in = v cc v in = gnd 60 100 m a/ mhz i c total power supply current (6) v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 0.6 1.5 ma x oe = gnd fi = 5mhz 50% duty cycle one bit toggling v in = 3.4v v in = gnd 1.1 3.0 v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 3.0 5.5 (5) x oe = gnd sixteen bits toggling fi = 2.5mhz 50% duty cycle v in = 3.4v v in = gnd 7.5 19.0 (5)
5.8 6 idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges switching characteristics over operating range fct16374t/162374t fct16374at/162374at com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay xclk to xox c l = 50pf r l = 500 w 2.0 10.0 2.0 11.0 2.0 6.5 2.0 7.2 ns t pzh t pzl output enable time 1.5 12.5 1.5 14.0 1.5 6.5 1.5 7.5 ns t phz t plz output disable time 1.5 8.0 1.5 8.0 1.5 5.5 1.5 6.5 ns t su set-up time high or low, xdx to xclk 2.0 2.0 2.0 2.0 ns t h hold time high or low, xdx to xclk 1.5 1.5 1.5 1.5 ns t w xclk pulse width high or low 7.0 7.0 5.0 6.0 ns t sk (o) output skew (3) 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. 4. this limit is guaranteed but not tested. 2542 tbl 09 fct16374ct/162374ct fct16374et/162374et com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay xclk to xox c l = 50pf r l = 500 w 2.0 5.2 2.0 6.2 1.5 3.7 ns t pzh t pzl output enable time 1.5 5.5 1.5 6.2 1.5 4.4 ns t phz t plz output disable time 1.5 5.0 1.5 5.7 1.5 3.6 ns t su set-up time high or low, xdx to xclk 2.0 2.0 1.5 ns t h hold time high or low, xdx to xclk 1.5 1.5 0.0 ns t w xclk pulse width high or low 5.0 6.0 3.0 (4) ns t sk (o) output skew (3) 0.5 0.5 0.5 ns
idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges 5.8 7 definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test circuits and waveforms test circuits for all outputs enable and disable times propagation delay set-up, hold and release times pulse width switch position test switch disable low enable low closed all other tests open open drain notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns 2542 drw 09 2542 lnk 10 pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. 2542 drw 05 2542 drw 06 2542 drw 08 2542 drw 07
5.8 8 idt54/74fct16374t/at/ct/et, 162374t/at/ct/et fast cmos 16-bit register (3-state) military and industrial temperature ranges ordering information idt xx temp. range xxxx device type x package x process blank b pv pa pf e 16374t 16374at 16374ct 16374et 162374t 162374at 162374ct 162374et commercial mil-std-883, class b shrink small outline package (so48-1) thin shrink small outline package (so48-2) thin very small outline package (so48-3) cerpack (e48-1) non-inverting 16-bit register 54 74 C55 c to +125 c C40 c to +85 c fct 2542 drw 10
|
